Coin-Op Collection Announcement: 2025 Roadmap

I’d like to take a moment to share some updates on our plans and current progress as the Z/Y-Unit cores are coming to a close. While we have additional projects slated that aren’t listed here, the summary below should give everyone a good sense of where we’re headed and what to expect.

There’s a lot to digest, so please take the time to read through everything. Darren, Pramod, Brandon, and I will be sharing updates about each project as development continues to keep you informed. Thank you to all of our supporters. Without you, none of this would be possible!

Open-Source FPGA Framework

Our FPGA framework will be open-source and is designed to simplify the creation of a "game core," offering web-based GUI utilities and templates for streamlined configuration. It features variable SDRAM and PSRAM controllers for flexible memory management, making it ideal for diverse 32-bit FPGA platforms. Created with versatility in mind, the framework will support multiple platforms, starting with the Analogue Pocket.

We're dedicating November and the early part of December to framework development and then we'll move forward with open-sourcing the code and a few examples. Some may be old, some may be new!

Framework Overview:
    • High performance SDRAM and PSRAM controllers for more intensive memory-demanding cores
    • User-friendly web-based tools provide a visual interface for configuration, offering a solid starting
       point for building and customizing a game core
    • Easy-to-use and reconfigurable framework for post-template generation, adaptable for growing
       needs such as multi-platform and peripheral/device support
    • Easy-to-follow video tutorials and comprehensive documentation to guide new users through
       usage and core creation, with the flexibility to expand and add content as needed

Upcoming FPGA Development

Our FPGA implementation roadmap is outlined below. This should clarify what our "major" projects and plans are for 2025. We have additional open-source FPGA cores planned, which, while not as popular as the development highlights listed, are definitely worth the time to research and develop.

Capcom ZN-1 FPGA compatible Verilog core

Brandon is steadily making progress on his ZN-1 hardware implementation. This month, he'll be wrapping up the remaining schematic extraction for the main motherboard. Below, you'll find progress on schematic extraction and gerber files for the main motherboard, along with the completed schematics for the ROM board. Brandon has completed tracing his die shot image of the DL-3129 and has extracted schematics for it as well. We've decided to follow this process for all future schematic extractions, which will include gerber files, whether done in-house or outsourced to a reverse engineering company.

The reverse engineering company we plan to use for the CPS-III project successfully extracted the FPGA bitstream from the CPDL (Altera EPM7032) on the ZN-1 main board. The next steps for ZN-1 involve writing Verilog and assembling the hardware architecture within our new framework. Once completed, this implementation will branch out to several other Sony-based arcade platforms. We'll update you on the progress of ZN-1 over the winter.

Hardware Overview:
    • Sony CXD8530BQ (CPU, R3000A-compatible)
    • Sony CXD8561Q (GPU, Toshiba)
    • Sony CXD2922CQ (SPU)
    • Zilog Z80 CPU (Sub-CPU)
    • DL-1425 (DSP, QSound)
    • DL-3129 (Ricoh Custom, Kick-Bus I/O Management)

An FPGA-compatible core with custom program ROMs, as well as the published program ROMs listed below.

    • Battle Arena Toshinden 2
    • Star Gladiator Episode I: Final Crusade
    • Gallop Racer
    • Street Fighter EX
    • Street Fighter EX Plus

Altera EPM7032 Bitstream Testing:

Sony COH-1000 Motherboard:

Capcom 95681-2 ROM Board:

Capcom DL-3129 Die Trace:

Capcom CPS-III FPGA compatible Verilog core

We've already begun our own research and development for CPS-III hardware, below you see our die-shot images of each ASIC for routing and tracing.

The DL-3229 will need to be reimaged as it cracked during the process. Brandon Arnold is spearheading the reverse-engineering process, working closely with a company that specializes in reverse engineering.

Not only will we be providing our own schematics, we'll also be including gerber files for the PCB and security cartridge. Pramod and I will start writing Verilog this winter and alternate between Toaplan V2, T-Unit, and CPS-III.

Hardware Overview:
    • DL-3229 SCU (Main CPU ASIC - Hitachi SH-2)
    • DL2829 CCU (Sub-CPU ASIC)
    • Capcom DL-2729 PPU (GFX ASIC)
    • DL-2929 (I/O Controller ASIC)
    • DL-3329 SSU (Sound ASIC)
    • DL-3429 (DMA Controller ASIC)
    • DL-3529 (SIMM Bank ASIC)

An FPGA-compatible core with custom program ROMs, as well as the published program ROMs listed below.

    • Warzard
    • Street Fighter III: New Generation
    • Street Fighter III 2nd Impact: Giant Attack
    • Street Fighter III 3rd Strike: Fight for the Future
    • JoJo no Kimyou na Bouken
    • JoJo no Kimyou na Bouken: Mirai e no Isan









 

Midway T-Unit / Wolf Unit FPGA compatible Verilog core

Development for the T-Unit hardware has begun. Upon completing the T-Unit ADPCM hardware variant, Pramod will implement the DCS sound system DSP, which is also used for audio playback in a wide range of Williams and Bally pinball machines.

We estimate it will take roughly 30 to 45 days to complete the ADPCM variant and 90 days to reverse engineer and implement the ADSP2105 DSP. Once the T-Unit is finished, we will begin work on the DMA handler and hardware configuration for the Wolf Unit hardware.

ADPCM (Adaptive Differential Pulse-Code Modulation) Hardware Overview:
    • Texas Instruments TMS34010
    • Motorola MC6809
    • DMA Handler
    • OKI MSM6295
    • Texas Instruments MC1408P8
    • Yamaha YM2151
    • Yamaha YM3012

DCS (Digital Compression System) Hardware Overview:
    • Texas Instruments TMS34010
    • DMA Handler
    • ADSP2105 DSP

An FPGA-compatible core with custom program ROMs, as well as the published program ROMs listed below.

T-Unit Hardware:
    • Mortal Kombat
    • Judge Dredd
    • Mortal Kombat II (DCS Based)
    • NBA Jam
    • NBA Jam Tournament Edition

DCS (Digital Compression System) Hardware Overview:
    • Texas Instruments TMS34010
    • DMA Handler
    • ADSP2105 DSP

An FPGA-compatible core with custom program ROMs, as well as the published program ROMs listed below.

Wolf Unit Hardware:
    • Mortal Kombat 3
    • WWF: Wrestlemania
    • Ultimate Mortal Kombat 3
    • Open Ice Challenge
    • NBA Hangtime
    • NBA Maximum Hangtime
    • Rampage: World Tour

Toaplan V2 FPGA compatible Verilog core

We've completed the majority of development for Toaplan V2 hardware; however, some components still need to be modeled, namely the NEC V25. We’ll be revamping the core structure, implementing the dual GP9001 design, and leveraging the SDRAM and PSRAM controllers from our framework to improve memory bandwidth, with the missing components to be modeled in Verilog.

Hardware Overview:
    • Motorola M68000 (Main-CPU, board dependent)
    • Zilog Z80 CPU (Sub-CPU, board dependent)
    • Hitachi HD647180 (Sub-CPU, board dependent)
    • NEC V25 (Sub-CPU, board dependent)
    • OKI MSM6295 (Board dependent)
    • Yamaha YM3812 (Board dependent)
    • Yamaha YM2151 (Board dependent)
    • Yamaha YM3012 (Board dependent)
    • GP9001 (GFX ASIC)
    • Dual GP9001 (GFX ASICs; board dependent)

An FPGA-compatible core with custom program ROMs, as well as the published program ROMs listed below. Titles below in bold have yet to be implemented due to missing components.

Schematics and gerber files are currently being developed by Brandon Arnold for Armed Police Batrider. Schematics for Knuckle Bash and Verilog source code are freely available for both hardware platforms (Toaplan2 / Raizing).

Toaplan2 Hardware:
    • Ghox
    • Dogyūn!!
    • Knuckle Bash
    • FixEight
    • V-V
    • Batsugun
    • Teki Paki (Released)
    • Tatsujin Ō (Released)
    • Whoopee!! (Released)
    • Otenki Paradise: Snow Bros. 2 (Released)

Raizing Hardware:
    • Mahou Daisakusen (Released)
    • Shippu Mahou Daisakusen (Released)
    • Battle Garegga (Released)
    • Armed Police Batrider (Released)
    • Battle Bakraid (Released)


Often, I see people mention Namco Pre-86 and Namco86 hardware. Mr. X was kind enough to share his source code with me and other MiSTer-devel developers. To date, none of those with access to the original source code have released Pac-Land.

We stepped aside after seeing another developer state they were creating the Namco86 core back in January of this year. Since that hasn't surfaced, and we had other ongoing projects, we've moved on.

I, in turn, passed the original source to the author of OpenGateware, boogerman, who successfully ported it. He plans to release Pac-Land after resolving issues and making optimizations to the port.

                                                         




Disclaimer: 
All product names, trademarks, and registered trademarks mentioned are the property of their respective owners. "Texas Instruments," "Hitachi," "Sony," "Motorola," "Yamaha," "OKI,"NEC", "Zilog," "Analog Devices," "Analogue," "Analogue Pocket," "Capcom," "Namco," "Toaplan," "Midway," "Raizing," "Lucky Land Communications," and all derivative works are trademarks, registered trademarks, or copyrighted materials of their respective holders. Use of these names does not imply endorsement or association with this post. All rights reserved to their respective owners. This post is for educational and research purposes only.