Coin-Op Collection Presents: Z-Unit (RC2) & Y-Unit (RC3)

Over the weekend, we released improvements to both the Z-Unit and Y-Unit cores. Below, you'll find information on the overall hardware overview, fixes, necessary optimizations, and our current release schedule for this phase. We have also implemented requests such as analog control support for Smash TV and Total Carnage, pause functionality, additional cheat options, and sound mix adjustments to CVSD and ADPCM. If you're interested in more details beyond what's provided here, check out Pramod's Twitch stream.

This week, we began working on our open-source "game core" framework, which will be published upon completion and is expected to take roughly 30-45 days to implement. We'll provide documentation on how to use the framework with tutorials and illustrate it with examples from the Technos16 core and others in development.

The key has been updated. Please ensure that key fetching remains enabled in pupdate. Currently, there are other updaters for the Analogue Pocket that support our automated platform, but we do not have direct communication with those authors. We do, however, receive support from the authors of pupdate. If you were a patron prior to the key change and are no longer a subscriber, the previous builds (dated 11/1/24) have been uploaded to GitHub.

The files may have been overwritten if you disabled key fetching after retrieving them originally, even if you are a current subscriber. If you experience issues, please fetch the updated key. If you'd like to retrieve files for this weekend's update manually, you can do so from GitHub. We will work with the authors of pupdate to find a solution for this in the future.

If you experience compatibility issues, please report them on the Coin-Op Collection Discord, as support cannot be provided on this platform. Out of over 500 users, only 15 have reported device compatibility issues, with two cases currently unresolved. Reported compatibility issues result in a 97% success rate for Analogue Pocket devices distributed via pupdate, which is significantly high given how the SDRAM is overclocked 33% faster than any other core using CAS 2 latency.

We'll see the next release candidate for the Y-Unit implementation on 11/16/24 and I'll be posting our 2025 project roadmap in the coming days. Have a great week everyone!

Williams Z-Unit FPGA compatible Verilog core

Hardware Overview:
    • Texas Instruments TMS34010
    • Motorola MC6809
    • Motorola MC6809
    • DMA Handler
    • Harris HC-55564
    • Texas Instruments MC1408P8
    • Texas Instruments MC1408P8
    • Yamaha YM2151
    • Yamaha YM3012

An FPGA-compatible core with custom program ROMs, as well as the published program ROM listed below. Service information, schematics, and source code are freely available for reference.

    • Narc (Released 9/7/24)

Williams / Midway Y-Unit FPGA compatible Verilog core

CVSD (Continuous Variable Slope Delta-Modulator) Hardware Overview:
    • Texas Instruments TMS34010
    • Motorola MC6809
    • DMA Handler
    • Motorola MC6821
    • Harris HC-55564
    • Texas Instruments MC1408P8
    • Yamaha YM2151
    • Yamaha YM3012

An FPGA-compatible core with custom program ROMs, as well as the published program ROMs listed below. Service information, schematics, and source code for Smash TV and Trog are freely available for reference.

    • Smash TV (Released 9/21/24)
    • High Impact Football (Pending Release 11/28/24)
    • Trog (Pending Release 11/16/24)
    • Super High Impact (Pending Release 11/28/24)

ADPCM (Adaptive Differential Pulse-Code Modulation) Hardware Overview:
    • Texas Instruments TMS34010
    • Motorola MC6809
    • DMA Handler
    • OKI MSM6295
    • Texas Instruments MC1408P8
    • Yamaha YM2151
    • Yamaha YM3012

An FPGA-compatible core with custom program ROMs, as well as the published program ROMs listed below. Service information, schematics, and source code for Total Carnage are freely available for reference.

    • Terminator 2: Judgement Day (Pending Release 12/25/24) 
    • Total Carnage (Released 11/02/24)
    • Mortal Kombat (Released 10/8/24)

Technical Challenges:

Two of the most difficult bugs to determine while verifying instructions and program ROM execution in the Texas Instruments TMS34010 Verilog CPU implementation were a move field instruction (1) and ensuring DMA width and height protection from becoming negative (2).

Move Field - Indirect to Register Issues (1):

• Unable to perform stage finishing move

• Special move ends in game over when making contact with player/cpu

• Incorrect text displayed when facing female character

• Player/CPU defeated with one-hit, whether using block or not

• Endurance match does not proper text but will let you perform a finishing move before facing final characters

• Unable to face the secret character

Looking at the information below, the execution process described in the manual indicates that the instruction first moves the data located at the memory address stored in the source register (Rs) to the destination register (Rd). After the transfer, the source register (Rs) is incremented by the size of the field that was moved. This means the source register will now point to the next field in memory, facilitating sequential data access in subsequent operations.



Looking at the source code from FBNeo shown below revealed that the instruction actually operates in reverse. It increments the source register (Rs) first, and then sets the destination register (Rd) to the original value. Typically, the source and destination registers would be separate, so the order does not matter. However, in this case, the source and destination fall on the same register.



Implementing this particular instruction the way it is emulated in FBNeo rectified the issues above (1). As source code is not published for any program written by Ed Boon, finding this nuance would have been impossible without referring to an emulator. As it were, this was already a needle-in-a-haystack situation.

Thankfully, there were clues indicating which instruction might be involved when facing the final character, this helped us narrow down what the issue may have been. Initially, I suspected it may have been a move byte instruction, but that turned out not to be the case. The TMS34010 has over 39 distinct move instruction variants, making this a challenge to pinpoint the exact operation.

DMA height and width protection (2):

• Vertical stripe would be generated when performing a stage finishing move

• Halted two additional program ROMs from execution when x-pos would draw the playbook

The other issue arose from height and width protection during DMA drawing. Similar to the problem mentioned earlier, this occurred in programs written by Ed Boon. Although the DMA rowbyte calculations were accurate and the x/y positions were correctly applied, there was no safeguard to prevent the width and height values used by the DMA from becoming negative.

When executing a stage finishing move, the negative height value caused the drawing to extend up to 2,000,000 pixels vertically instead of being limited to 256, resulting in a vertical stripe being rendered. Making the minor changes shown below resolved the issue.

SDRAM Controller Optimizations:

Another significant challenge that made Z-Unit/Y-Unit unplayable was related to SDRAM speed. By running the SDRAM at 128 MHz with a single-transaction 48-bit write while using a CAS (Column Address Strobe) latency of 2, the Z-Unit/Y-Unit implementations became feasible for the Analogue Pocket. This required substantial modifications to the SDRAM controller, which initially supported only single-transaction 16-bit writes.

The optimal frequency for CAS latency 2 is specified as 83 MHz in the datasheet, and traditionally, 96 MHz has been considered the maximum safe speed for both the Analogue Pocket and MiSTerFPGA. Fortunately, Pramod successfully pushed the SDRAM to a maximum throughput of 128 MHz and implemented further optimizations to reduce DMA transaction times, achieving a performance gain of approximately 164 ns, ultimately meeting the required timing constraints.

For example, a hang could occur when executing a stage finishing move if DMA height overflowed due to a lack of protection. This issue caused the DMA to run overtime, resulting in continuous writes that persisted even with the improved settings of a single-transaction 32-bit or burst 32-bit write at CAS latency 2 with 128 MHz operation. The glitch could sometimes last up to 120 seconds before recovery. Another instance of this optimization challenge was the flickering effect observed in specific stages of the Z-Unit implementation.

Core Features:

Below are the available CMOS options for the Z-Unit. In addition to game settings, there are cheat settings. While cheats are available for the Z-Unit, they overwrite program memory and program ROM locations when addressed by the TMS34010 CPU. If you encounter a bug, ensure that cheats have not been selected.



Below are the available CMOS options for the Y-Unit. The default settings are configured to skip POST checks upon boot, which will display a black screen. Press any button other than "Coin" to continue the boot process. In addition to the game test menu, there are cheat settings. While cheats are available, they overwrite program memory and program ROM locations when addressed by the TMS34010. If you encounter a bug, ensure that cheats have not been selected.










Disclaimer: 
All product names, trademarks, and registered trademarks mentioned are the property of their respective owners. "Texas Instruments," "Motorola," "Harris," "Yamaha," "OKI," "Analogue," "Analogue Pocket," "MiSTer FPGA," "Technos," "Williams," "Midway," "Narc," "Smash TV," "High Impact Football," "Trog," "Super High Impact," "Terminator 2: Judgement Day," "Total Carnage," "Mortal Kombat" and all derivative works are trademarks, registered trademarks, or copyrighted materials of their respective holders. Use of these names does not imply endorsement or association with this post. All rights reserved to their respective owners. This post is for educational and research purposes only.