Progress October I - Long time no see & another milestone reached
Added 2016-10-02 05:54:26 +0000 UTCAnd I thought that I'd post updates 6 weeks apart at the very worst...At least I have some news to bring !
First of all, about the hardware: I will finally be ordering the 4-layer FPGA board as soon as the pledges for this update are processed. The components are still waiting in their trays for now.
I didn't get much done on the motherboard itself, as I wanted to dedicated some time to checks and to the addition of patch/bodge points on the FPGA board in case I mess up. That's done now.
Secondly, the real good news is about the Verilog code itself (see Github).The code is now accurate enough to run the system ROM (aka BIOS) up to the game's entry point !This may not seem that exceptionnal, but it really means that the logic and memories are working well enough to pass the self-tests and start executing game code.
As shown on the screenshot, the simulation log indicates that a jump to the game's entry point was taken after 220ms of what would be real time.If you're wondering why 220ms instead of the usual 3~4 seconds startup time of a real MVS board, it's because I patched the SP-S2.SP1 system ROM to greatly shorten memory test loops. If 256 bytes of RAM pass the test, no need to check the next 65280... This allows the simulation to be done in 10 minutes instead of many days of continuous computation.
The next step before letting the game run and see what happens would be to dump memories and compare the contents with a MAME snapshot under the same initial conditions.
