XaiJu
furrtek
furrtek

patreon


Progress April - IV : Summing up

Is it May already ? This is a paid post. Thanks everyone for your support :)

Here are the latest news, what has been done and what needs to be done:


Regarding logic:

I recently moved blocks around NeoGeoFPGA-sim to make the NeoGeo core and auxiliary logic separation clearer, the goal is to simplify things when I'll need to make the design synthesizable for the verification board.

Elementary logic was added or refined in NEO-C1  such as mirroring ranges, unmapped zones, and wait state generation.

Two important additions which aren't directly NeoGeo related are video and audio interfaces: In an earlier post I wrote that I wanted to use an ADV7125 video DAC. 


When recuding the outside world connections (FPGA I/Os), I realized that the count was still dangerously close to 200, and the 23 lines required for the ADV7125 weren't helping. Also, the ADV7125's regular steps between color intensity levels wouldn't be very faithful to the original NeoGeo ghetto R2R DAC.

Here's my solution: serialize the parallel color data in the FPGA, output the 3 serial streams, make them parallel again with 74VHC595 SIPO registers and feed their outputs to the R2R DAC.

Benefits: Saves 18 outputs. Rendering logic is untouched. Can exactly match the color levels of the NeoGeo.

Drawbacks: PISO/SIPO interface introduces a 0.5 pixel delay.

For the audio output, no change: it will be I2S for the planned AK4430 DAC.

No real progress on video, still have to figure out if the fix is rendered with a 4 or 8 pixels delay from fetch to display (not that hard).


Regarding hardware

:

More progress on the hardware as shown in the post picture: the FPGA SODIMM module is almost routed, and I might be able to order the board (x3) and parts at the end of the month.


To-do in May:

Progress April - IV : Summing up

More Creators