Progress March - I
Added 2016-03-04 14:10:34 +0000 UTCThese last days consisted of blind-writing verilog with inspiration from the neogeodev wiki and MAME's source. Started hooking up the ao68000 68k CPU core yesterday, to test bus control and address decoding.
The first step will be to have the system ROM run at least up to the MVS self-checks. This should happen shortly, as the only problem I have now is with understanding the 32-bit access done through the Wishbone interface.
I'll write a paid update when I'll be able to prove correct execution up to the checks.
https://github.com/neogeodev/NeoGeoFPGA-sim
