Setting things up
Added 2016-02-27 19:03:33 +0000 UTCThis is a free post, nobody will be charged for this month.
Thanks to your support, I'll be able to make some CPLD boards with practical connectors to validate the definition of some of the simpler SNK chips.
I've set up the Github repository for simulation files here:
https://github.com/neogeodev/NeoGeoFPGA-sim
Simulation means that the first step is to get most of the design working by software simulation, no need for hardware yet.
This is done by writing NeoGeo chips definitions, testbenches and asking the simulator software to show how everything would behave as if it ran in a real FPGA.
For example, we can make a pre-filled VRAM model, connected to a sprite controller model, which outputs data to a line buffer model, which outputs data to a palette RAM model, which outputs a picture.
Seems complicated for not a whole lot, but that's how the console works !
I'll be using ISE and ISim from Xilinx, because I'm planning on using a Spartan 6 FPGA for the dev board.
Check out the repo later on today for the first commit, which will mainly be plugging Verilog modules in each other to organize the console's hierarchy.
