So I've been trying to find a combination of microcontrollers, DACs and ADCs that can operate 3 OSMU channels (= 12 DACs + 6 ADCs + a few digital pins) simultaneously, with reasonable speed (= hundreds of kHz or even a few MHz?) and are easy to opto-isolate.
There are some attractive all-in-one solutions here: http://www.analog.com/en/parametricsearch/11289 or http://www.ti.com/product/LMP92018 or https://www.maximintegrated.com/en/products/analog/data-converters/analog-to-digital-converters/MAX1329.html
But my initial plan of controlling all 3 channels with 1 SPI bus seems totally unrealistic.
1. Option: An STM32F302 on every output stage. It has fast ADCs and DACs and it could get its program from a central UI controller before running. It would need clock distribution tho and data output would have to happen sort of asynchronously.
2. Option: A central Xilinx Zynq which is an ARM Cortex-A9 for the UI and connectivity and FPGA for the high pin count, high speed control of all the discrete DACs and ADCs. It needs a lot of digital isolators and the component itself is not cheap.
Personally I like the second option better, because I've been making excuses for not learning FPGA stuff for far too long. It's also easier for firmware updates and I don't think it would scare away community software developers - they can just have their way with the SoC and never even touch the FPGA side.
Thoughts?
I also want to connect the output stages via PCI-E or some other card edge connection, so that users can replace them, or swap high-current / high voltages modules later ...
Vinicius Miguel
2019-08-17 15:25:37 +0000 UTCMarco Reps
2018-07-11 22:51:05 +0000 UTCDillon Nichols
2018-07-10 14:22:07 +0000 UTCVolodymyr Babchuk
2018-07-09 12:23:40 +0000 UTCTweakoZ
2018-07-08 08:54:46 +0000 UTCMarco Reps
2018-07-08 08:47:43 +0000 UTCTweakoZ
2018-07-07 22:52:02 +0000 UTCJan-Henrik Bruhn
2018-07-07 21:54:43 +0000 UTCJan-Henrik Bruhn
2018-07-07 16:47:19 +0000 UTCMarco Reps
2018-07-07 16:42:17 +0000 UTCJan-Henrik Bruhn
2018-07-07 16:34:41 +0000 UTCJason Wilson
2018-07-07 16:28:07 +0000 UTCMarco Reps
2018-07-07 16:27:00 +0000 UTCJan-Henrik Bruhn
2018-07-07 16:11:37 +0000 UTC