furrtek

Progress January I - Something meaningful (paid post)

Finally something meaningful for those who simply want to enjoy playing games without thinking about the technical stuff:

We have a basic NeoGeo core for MiSTer running !

Take a look at the video. There's no commentary at all so you can skip through it as I try a few of the smaller games (and one not that small).

The first obvious point is that there's no audio for now. I'm planning to hook up Jotego's YM core soon to at least get the SSG and FM channels going. The ADPCM par...

Progress November I - A small blue board shows up

I finally yielded to pressure from the many e-mails and tweets asking if a MiSTer core was going to be made for the NeoGeo :(

Just joking, it was a decision :)
A decision which was rather easy to take in the end, since it doesn't change anything to the original project's goals.
I was initially reluctant about taking this road because of my unfamiliarity with SDRAM and the fear of having to change the core logic to compensate for latency.

What really made me take the first step is S...

Progress October I - Real FPGA gets some use

Short video update as I didn't have much time to spend on the project these last months. I did get a minimal setup to run on the Terasic DE-1 dev board (Altera FPGA).

It runs the TG68k 68000 core, the reverse-engineered LSPC2-A2 and NEO-B1 video chips, along with various SNK chips for glue logic, decoding, I/O...

The small program sets up fix tiles and sprites in VRAM and allows to move a block with the joypad. The shrinking parameters can also be modified to check that the logic works c...

Progress June I - Component placement

Quick update with a pretty bad looking 3D preview of the testing board.

Routing is done locally but the groups aren't connected together yet, so stuff can (and will) still be moved around.

To reduce the number of I/Os needed on the FPGA board (which will be stuck vertically), I'm using an additional CPLD to do address decoding. That way it can just sit on the already available 68k address bus, and output enable/clock signals to a bunch of HC245's which will gate data to and from the data...

Progress April II - Eye-catcher runs !

Here it is ! After I finished tracing the NEO-B1 die picture earlier than I thought (lots of parallel stuff in it), I translated the schematic to verilog and spent about 5 days trying to get the simulation to start up Metal Slug and display the iconic eye-catcher animation.

Two bugs were caused by missing characters: One "&" causing glitches on horizontally scaled sprites, and one ~ preventing sprite chaining from working.
Another bug was caused by the 68k core I'm using (TG68K) not lik...

Progress April I - Heartbeat

I'm still alive and the tracing of NEO-B1 is going smoothly.
I should be able to start translating the schematic to Verilog next month.

No surprises in this chip, everything is pretty straightforward except for a few odd uses of shift registers I wouldn't have guessed. Also lots of logic is used up by a test mode giving direct access to the SRAM cells. This was certainly used before assembly to see if no bits were faulty.

Lots of silicon for something that was only used once at the fa...

Progress March I - NEO-B1 tracing

John got to image NEO-B1, the second chip responsible for video on the NeoGeo: https://siliconpr0n.org/map/snk/neo-b1/mz_mit20x/

It is known to mostly contain SRAM making the pair of line buffers needed to render sprites. Interestingly, unlike LSPC, this is a standard cell ASIC. There aren't any markings except for "87815", which probably doesn't mean anything outside of Fujitsu's offices.

I couldn'...

Progress February II - LSPC2 schematic

I just exported all the LSPC2 schematic sheets to png files and pushed them to Github: https://github.com/neogeodev/NeoGeoFPGA-sim/tree/master/LSPC2RE

As the Readme says: don't expect everything to be correct, I'm sharing this just to show progress. Some parts were thoroughly checked because they were causing simulation to give incorrect results, but most are not !

Speaking of simulati...

Progress February I - Tracing done !

It took about 110 hours to completely trace the LSPC2 chip die and draw the schematic using symbols representing the cells.

As already said, my wrist was giving up sometimes but it always recovered after some sleep, so no serious damage there :)
Apart from a few tedious fixes, it really wasn't that much of a pain thanks to the very clear pictures John took.

You can navigate the rendered picture here:

http://furrte...

Progress January II - Untangling spaghetti

I've spent 56 hours until now identifying cells and tracing metal in LSPC2-A2 (the main video chip) and things are going smoothly, even if I had to take extended breaks because of wrist and shoulder pain :p
Might have to adjust my desk...

Attached to this post is a collage of the current schematics sheets I "translated" from the die.

For now there are no surprises, no "unused bits" actually doing something, no hidden registers. The only realization is that I could have hardly guessed ...

Progress January I - Metal spaghetti

The high-resolution die picture of LSPC (the NeoGeo video controller chip) is here !

John McMaster submitted it to his website siliconpr0n.org just a few days after receiving the envelope from France, right between Christmas and new year's eve.

I've wondered for years (no joke) if it was possible to figure out everything by just looking inside and it turns out to be !
Coïncidentally, ArcadeHacker just wrote a blog post about a CPS2 chip of a very similar series: 2018-01-03 15:27:42 +0000 UTC View Post

Progress December I - More silicon nudes

Guesswork does get elements to function individually, but piecing them together often reveals that they're not that accurate because they don't stick as a whole.

I was bitten by this more than once in this project mostly because phases of different signal groups didn't match. Checking signals multiple times to see if I wasn't hitting an unknown corner case or if I messed up while taking notes or naming files.

Frankly, most of the time, the notes were correct and I was just taking wrong g...

Progress October I - Sprites starting to show up

Almost 6 months without an update, nothing unusual or unplanned... :)

Here's something for the eyes: progress of the video output spit out by the logic simulation. Sprites (almost everything except text on the NeoGeo) are starting to show up in the right positions and with mostly the right colors.

This is still generated from VRAM and palette RAM captures from MAME, since I can't let the simulation run long enough for the game to reach the title screen.

I'm not 100% sure Metal Slug...

Progress May I - Sprites & (french) talk

Last week-end, I attended a french arcade event organized by HFS (https://www.hfsplay.fr/). I met great, passionate people, played very Japanese games, ate sandwiches, saw a bunch of CPS2's and... gave a short talk about this project in front of ~30 people.

I reached my only goal: I didn't faint !

Apart from that, it was very motivating to show the project "live", instead of posts here or on Twitter. Especially later on, w...

Progress March II - Fix layer 100%

If you recall one of the first posts, I showed the video output of a simulation which rendered Puzzled/Joy Joy Kid's fix layer (used for text, HUDs, scores, lifebars...). 

That was done with only 2 constraints: to use real memory snapshots (real ROM and VRAM snapshot from MAME), and to have a pixel-perfect output.

That being said, this picture of my DE1 FPGA board rendering a similar image from Metal Slug 1 might  not seem like anything new.
That's because the added constrai...

Progress March I - More schematics

Still working from time to time on the project. I recently did some schematic drawing and coarse component placement on the main board.

External memories, video and audio DAC, and basic I/O like debug UART, joypads, memory card, marquee and LED outputs, coin mech control, ... are done.

I still didn't have the courage to order the FPGA board, so I might instead order the main board first (with the same money from Patreon) and see how the board house quality turns out.

Also did some ...

Progress January I - Silicon nudes

Getting back to work on the project now that the move's over with.

Got the first die pictures of the revered YM2610 and started tracing some easy stuff.

Yamaha's FM logic isn't that obscure thanks to the work of other people. With these new pictures, it should be possible to know exactly how the ADPCM logic works.
I'll be posting annotated pictures of different zones to Github soon.

I didn't order the FPGA board in the end, as I didn't want to complicate things with the address ...

Progress November I.5 - Code update & silicon curiosity

The preliminary YM2610 ADPCM and timers code is on Github, and a few YM2610 were sent to someone who has hydrofluoric acid and a good microscope :)

Also sending the FPGA board to fab next week.

Progress November I - Music with real instruments

Didn't expect to get this part of the YM2610 done before the SSG ! Maybe because the SSG is mainly used just for the coin-in sounds...

Anyways, I shot this video a few days ago and didn't write a progress report here because I wanted to get the ADPCM-B to work (all ADPCM channels). I then realized it would take a few more days so here it is. There will probably be an small update to this, with the missing melody ;)

I will also update the Github repo later, since I'm using my Altera devbo...

Progress October II.5 - Strip tease

Spent 2 hours stripping a dead MV4 board I had since years.

This will greatly help verify and simplify logic for the NEO-D0, NEO-F0, and NEO-I0 chips.

Progress October II - Minor detail

Shortly after the last post, I noticed that there was quite an important shortcut taken to get the system ROM to start the game: the Z80 wasn't running properly.

The system ROM didn't give the familiar "Z80 ERROR" because I previously put a loopback register in NEO-D0 so that the 68000 read back the command it sent to the Z80, bypassing it completly. So in saying that everything was working well enough for the game to start, I lied ;)

The Z80 is now working properly, as well as NEO-D0 so...

Progress October I - Long time no see & another milestone reached

And I thought that I'd post updates 6 weeks apart at the very worst...At least I have some news to bring !

First of all, about the hardware: I will finally be ordering the 4-layer FPGA board as soon as the pledges for this update are processed. The components are still waiting in their trays for now.

I didn't get much done on the motherboard itself, as I wanted to dedicated some time to checks and to the addition of patch/bodge points on the FPGA board in case I mess up. That's done now....

Progress June I - More basics

After almost a month long break, I'm getting back to probing boards with the aim of finishing the basics: Reset, watchdog, address decoding, and video sync. I'm still discovering new stuff !

The Github repo is still being updated accordingly: https://github.com/neogeodev/NeoGeoFPGA-sim

I also have to finish up the FPGA board and order it. Should be able to do that before july.

The brains arrived safely

Back home, so just a quick post to show what I received from Avnet a few days ago.

As usual with big distributors, the parcel's size was inversely proportional to the component's.

From left to right: The CPLD which will replicate ZMC2 to save inputs on the FPGA, the FPGA, and its configuration memory.

Progress May - II : First delivery

I knew two things would happen: ridiculous customs fees, and package that arrives just when I leave. As predicted, I got a $60 bill from DHL (on a $140 order), and their delivery guy arrived 2 hours after I left for a few days trip. Luckily he knew the address: he signed for me and left the package in the mailbox.

This means that I won't have pictures of the FPGAs and CPLDs before Wednesday. Oh well :)

Progress May - I : Some intelligence

After losing half my hair at attempting to make AO68000 work, I gave up and followed the advice I was given: switch to TG68K.

Great news: after less than a day of work, I got it set up good enough to make the MVS system ROM (BIOS) pass the work RAM test !

It isn't that much of an achievement after all, it only means that:

• TG68K works
• NEO-C1's logic is good enough to make SROM and WRAM access work
• The read/writes to LSPC and a few other chips befo...
  2016-05-14 16:41:02 +0000 UTC View Post

Progress April - IV : Summing up

Is it May already ? This is a paid post. Thanks everyone for your support :)

Here are the latest news, what has been done and what needs to be done:

Regarding logic:

I recently moved blocks around NeoGeoFPGA-sim to make the NeoGeo core and auxiliary logic separation clearer, the goal is to simplify things when I'll need to make the design synthesizable for the verifi...

Thoughts about cost optimization and risks

Talking with a friend about FPGA development boards made me realize how painful it would be to have the FPGA fail on the verification board, knowing it would be in BGA and next to a bunch of other components.

$400 isn't that steep of a price for such a project, but burning up 3/4th of it by accident would be a big disappointment for everyone.

To minimize the risks, I came to consider a two-board solution:

* A big 2-layers board with all the connectors, 68k work RAM, flash, ...

Progress April - III : PCB work

Did some PCB work for the parts that won't be changing. Changed the 245 latches from SOIC to QFN to save space and reduce the board's size as much as possible.

Not sure if the memory card is a good idea, it stretches the board over 2cm.

No updates on logic for now.

Progress April - II : Hardware costs

Did some more component selection, most of the ICs are chosen.

Still nothing definitive, and the people making the IcoBoard informed me that their hardware might suit my needs. Decisions will have to be taken :)

Here's the current BOM if I chose to go for a completely custom board. Digikey part numbers are in parenthesis:

* XC6SLX16-2FTG256C (122-1672-ND) - Main FPGA

* XC9572XL-10TQG100C (122-1386-ND) - Graphics serializer CPLD, saves I/Os

* ADV7125 (ADV7125KSTZ50-N...