furrtek

Progress April - I : Faster waves

In the previous post, I wrote about Wavedrom to draw chronograms from obervations, measures and notes. I was already getting slowdowns due to the size of the data (not that big) and finally got to the point it became unusable.

Instead of desperately trying to make Javascript and SVG rendering in Chrome faster, I spent these last 6 days writing a standalone Wavedrom clone in VB6, using OpenGL for rendering.

Here it is: 2016-04-06 14:42:51 +0000 UTC View Post

Progress March - IV : More waves

Representing chronograms in Notepad started to get confusing.

While searching for a graphic editor, I discovered Wavedrom . It's a js application able to parse specially crafted JSON files to render chronograms as SVG.

The waves are defined as strings, where each character represents a "block". So switching from the text drawings I had to that particular format was quick and easy.

The amount of SVG data...

Progress March - III : Measurements

Instead of trying to guess the correct timings for the fix render cycle, I wired up the logic analyzer again and spent half the day recording everything between LSPC and B1. I now have 6kB worth of notes and many chronograms.

What comes up is just a confirmation that:

* The video logic is very simple compared to consoles of the time.

* Using both edges of a clock is crazy.

Now to match everything...

Some PCB work

Slowed down verilog work after finally breathing some fresh air.

Did some component selection, and a bit of schematic and PCB work for the test board, since it will be made. Thanks to Marshall H. for helping.

Progress March - II : Fix rendering works !

...from a tilemap snapshot ;)

In the last post I was aiming at making ao68000 run at least up to the MVS checks. I actually got fed up of trying to debug a poorly documented core, so I switched to specific NeoGeo stuff instead for this month.

Since I believe this can also be seen as a milestone, I'm making this a paid update. Thank you everyone :)

As you can see,...

Progress March - I

These last days consisted of blind-writing verilog with inspiration from the neogeodev wiki and MAME's source. Started hooking up the ao68000 68k CPU core yesterday, to test bus control and address decoding.

The first step will be to have the system ROM run at least up to the MVS self-checks. This should happen shortly, as the only problem I have now is with understanding the 32-bit access done through the Wishbone interface.

I'll write a paid update when I'll be able to prove co...

Setting things up

This is a free post, nobody will be charged for this month.

Thanks to your support, I'll be able to make some CPLD boards with practical connectors to validate the definition of some of the simpler SNK chips. 

I've set up the Github repository for simulation files here:

https://github.com/neogeodev/NeoGeoFPGA-sim

Simulation means that the first step is to get most of the d...